Yosys - A Free Verilog Synthesis Suite

Most of todays digital design work is done using hardware description languages such as Verilog HDL or VHDL. HDL synthesis is used to translate that HDL code to digital circuits. Yosys is the first free and open source software for Verilog HDL synthesis which supports the vast majority of synthesizable Verilog features. Yosys is built as an extensible framework so it can be used easily as basis for custom synthesis flows and as environment for the implementation and research on new synthesis algorithms. Yosys has special emphasis on support for coarse-grain logic, making it ideal for algorithms such as logic mapping to DSP cells in FPGAs or synthesis for custom coarse-grain reconfigurable hardware. Yosys has mature support for Verilog HDL and is able to synthesize complex real-world Verilog designs. Example design flows for fine-grain and coarse-grain architectures are presented and discussed. The availability of Yosys under a liberal open source license can greatly improve reproducibility of scientific publications, when Yosys is used as basis for reference implementations of new algorithms instead of closed-source alternatives.