Abstract
SystemVerilog Assertions (SVA) is an industry standard for specifying properties that describe the correct behavior of a system. Compared to SystemVerilog’s immediate assertions, they provide a much more powerful syntax including the ability to specify properties spanning over multiple clock cycles. However, to the best of our knowledge, SVA is not supported by any available open-source Electronic Design Automation (EDA) tool. In this paper, we present WSVA, a compiler from SVA to the Waveform Analysis Language (WAL).
| Original language | English |
|---|---|
| Title of host publication | Workshop on Open-Source Design Automation (OSDA) 2024 hosted at DATE |
| Number of pages | 2 |
| Publication status | Published - 2024 |
Fields of science
- 202005 Computer architecture
- 202017 Embedded systems
- 102 Computer Sciences
- 102005 Computer aided design (CAD)
JKU Focus areas
- Digital Transformation