System- and circuit-level optimization of PLL designs for DVB-T/H receivers

N. N. Tchamov; V. Syrjälä; J. Rinne; Mikko Valkama; Y. Zou; M. Renfors

doi:10.1007/s10470-011-9823-2

System- and circuit-level optimization of PLL designs for DVB-T/H receivers

N. N. Tchamov
, V. Syrjälä
, J. Rinne
, Mikko Valkama
, Y. Zou
, M. Renfors

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	185-200
Number of pages	16
Journal	Analog Integrated Circuits and Signal Processing
Volume	73
Issue number	1
DOIs	https://doi.org/10.1007/s10470-011-9823-2
Publication status	Published - Oct 2012

Fields of science

101 Mathematics
102 Computer Sciences
202 Electrical Engineering, Electronics, Information Engineering
202009 Electrical drive engineering
202027 Mechatronics
202034 Control engineering
202036 Sensor systems
203 Mechanical Engineering
203033 Hydraulic drive technology

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10.1007/s10470-011-9823-2

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title = "System- and circuit-level optimization of PLL designs for DVB-T/H receivers",

author = "Tchamov, \{N. N.\} and V. Syrj{\"a}l{\"a} and J. Rinne and Mikko Valkama and Y. Zou and M. Renfors",

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AU - Tchamov, N. N.

AU - Syrjälä, V.

AU - Rinne, J.

AU - Valkama, Mikko

AU - Zou, Y.

AU - Renfors, M.

PY - 2012/10

Y1 - 2012/10

UR - https://www.scopus.com/pages/publications/84866742513

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DO - 10.1007/s10470-011-9823-2

M3 - Article

SN - 0925-1030

VL - 73

SP - 185

EP - 200

JO - Analog Integrated Circuits and Signal Processing

JF - Analog Integrated Circuits and Signal Processing

IS - 1

ER -

System- and circuit-level optimization of PLL designs for DVB-T/H receivers

Fields of science

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