Abstract
We propose a fully-parallel low-complexity hardware architecture of a soft-input soft-output detector based on message passing on a factor graph. Conventionally, the message computation in the graph nodes consists of complex arithmetic operations on probabilities. Here, we represent probabilities by bit-serial streams and transform the arithmetic operations into simple bit-wise operations. This principle is known as stochastic computation and this is its first application to a detection algorithm. We evaluate the bit error rate (BER) performance of the stochastic detector by computer simulations of a communication system with intersymbol interference employing turbo equalization. The results show a performance loss of about 0.5dB at a BER of 10^-3 compared to the floating-point implementation of the detector.
Original language | English |
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Title of host publication | Signals, Systems and Computers (ASILOMAR), 2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems, and Computers |
Number of pages | 5 |
DOIs | |
Publication status | Published - Nov 2012 |
Fields of science
- 202030 Communication engineering
- 202038 Telecommunications
JKU Focus areas
- Mechatronics and Information Processing