Securing RISC-y computing with Goldcrest

The open standard RISC-V has created plenty of new possibilities for processor research, with the emphasis being on flexibility and openness. This thesis further builds upon previous work, namely the processor Goldcrest, a Verilog-based processor, which joins the compatibility of the RV32I RISC-V instruction set with the minimalism of the One Instruction Set Computer (OISC) principle. Goldcrest achieves this by hiding the main SUbtract and Branch if Less than or EQual to zero (SUBLEQ) core behind a microcoded RISC-V interface, which allows conventional compilers to target the system easily, while the processor design itself still preserves the simplicity of OISC.
The main contribution of this thesis is the systematic hardening of Goldcrest against side-channel attacks. The microcode has been formally verified to be functionally cor- rect, which was the basis upon which further safety measures were built. Timing based attacks were mitigated by implementation of RV32IZkt, which ensures data independent execution time at the hardware level. For power-based attacks, the standing hypothesis is that Goldcrest’s microcoded architecture is inherently more resistant to such attacks, due to less leakage. This is then examined through evaluation at the Register Transfer Level (RTL) level, and comparison with existing RISC-V implementations.