Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements

Yue Liu; Ulrich Vollenbruch; Yangjian Chen; Christian Wicpalek; Linus Maurer; Zdravko Boos; Robert Weigel

Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements

Yue Liu, Ulrich Vollenbruch, Yangjian Chen, Christian Wicpalek, Linus Maurer, Zdravko Boos, Robert Weigel

Institute for Communications Engineering and RF-Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

Abstract

This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 μm CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.

Original language	English
Title of host publication	Proceedings of the European Conference on Wireless Technology
Pages	347 350
Number of pages	4
Publication status	Published - 2007

Fields of science

202 Electrical Engineering, Electronics, Information Engineering
202019 High frequency engineering
202029 Microwave engineering
202030 Communication engineering
202033 Radar technology
202037 Signal processing
202038 Telecommunications

Cite this

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title = "Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements",

abstract = "This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 μm CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.",

author = "Yue Liu and Ulrich Vollenbruch and Yangjian Chen and Christian Wicpalek and Linus Maurer and Zdravko Boos and Robert Weigel",

year = "2007",

language = "English",

pages = "347 350",

booktitle = "Proceedings of the European Conference on Wireless Technology",

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T1 - Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements

AU - Liu, Yue

AU - Vollenbruch, Ulrich

AU - Chen, Yangjian

AU - Wicpalek, Christian

AU - Maurer, Linus

AU - Boos, Zdravko

AU - Weigel, Robert

PY - 2007

Y1 - 2007

N2 - This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 μm CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.

AB - This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 μm CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.

M3 - Conference proceedings

SP - 347 350

BT - Proceedings of the European Conference on Wireless Technology

ER -