Low phase noise 77-GHz fractional-N PLL with DLL-based reference frequency multiplier for FMCW radars

Herman Jalli Ng; Rainer Stuhlberger; Linus Maurer; Andreas Stelzer

Low phase noise 77-GHz fractional-N PLL with DLL-based reference frequency multiplier for FMCW radars

Herman Jalli Ng
, Rainer Stuhlberger
, Linus Maurer
, Andreas Stelzer

Department of RF-Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

Abstract

Two architectures of 77-GHz fractional-N phase-locked loops (PLLs) for FMCW radars are presented. Both architectures show good performance in terms of phase noise with -79 dBc/Hz at 100 kHz offset frequency. To achieve this, the integration of a delay-locked loop-based frequency multiplier for the reference signal in the PLL is proposed. It exhibits very low phase noise and proves to be an excellent alternative to other types of multipliers for lower frequencies.

Original language	English
Title of host publication	Proc. of the European Microwave Integrated Circuits Conference (EuMIC) 2011
Pages	196 - 199
Number of pages	4
Publication status	Published - Oct 2011

Fields of science

202037 Signal processing
202033 Radar technology

JKU Focus areas

Mechatronics and Information Processing

Cite this

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title = "Low phase noise 77-GHz fractional-N PLL with DLL-based reference frequency multiplier for FMCW radars",

abstract = "Two architectures of 77-GHz fractional-N phase-locked loops (PLLs) for FMCW radars are presented. Both architectures show good performance in terms of phase noise with -79 dBc/Hz at 100 kHz offset frequency. To achieve this, the integration of a delay-locked loop-based frequency multiplier for the reference signal in the PLL is proposed. It exhibits very low phase noise and proves to be an excellent alternative to other types of multipliers for lower frequencies.",

author = "Ng, \{Herman Jalli\} and Rainer Stuhlberger and Linus Maurer and Andreas Stelzer",

year = "2011",

month = oct,

language = "English",

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T1 - Low phase noise 77-GHz fractional-N PLL with DLL-based reference frequency multiplier for FMCW radars

AU - Ng, Herman Jalli

AU - Stuhlberger, Rainer

AU - Maurer, Linus

AU - Stelzer, Andreas

PY - 2011/10

Y1 - 2011/10

N2 - Two architectures of 77-GHz fractional-N phase-locked loops (PLLs) for FMCW radars are presented. Both architectures show good performance in terms of phase noise with -79 dBc/Hz at 100 kHz offset frequency. To achieve this, the integration of a delay-locked loop-based frequency multiplier for the reference signal in the PLL is proposed. It exhibits very low phase noise and proves to be an excellent alternative to other types of multipliers for lower frequencies.

AB - Two architectures of 77-GHz fractional-N phase-locked loops (PLLs) for FMCW radars are presented. Both architectures show good performance in terms of phase noise with -79 dBc/Hz at 100 kHz offset frequency. To achieve this, the integration of a delay-locked loop-based frequency multiplier for the reference signal in the PLL is proposed. It exhibits very low phase noise and proves to be an excellent alternative to other types of multipliers for lower frequencies.

UR - http://www.eumweek.com/2011/EuMIC.asp?id=c

M3 - Conference proceedings

SN - 978-1-61284-236-3

SP - 196

EP - 199

BT - Proc. of the European Microwave Integrated Circuits Conference (EuMIC) 2011

ER -

Low phase noise 77-GHz fractional-N PLL with DLL-based reference frequency multiplier for FMCW radars

Abstract

Fields of science

JKU Focus areas

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Cite this