FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers

Research output: Chapter in Book/Report/Conference proceedingConference proceedings

Original languageEnglish
Title of host publicationProceedings of Field Programmable Logic and Applications
Number of pages4
Publication statusPublished - Dec 2000

Publication series

NameLecture Notes in Computer Science (LNCS)

Fields of science

  • 101 Mathematics

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