FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers

Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings

Original language	English
Title of host publication	Proceedings of Field Programmable Logic and Applications
Number of pages	4
Publication status	Published - Dec 2000

Name	Lecture Notes in Computer Science (LNCS)

Fields of science

@inproceedings{05ce8ec1c83c4ebebc06af552ba623f7,

title = "FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers",

author = "Bogdan Matasaru and Tudor Jebelean",

year = "2000",

month = dec,

language = "English",

series = "Lecture Notes in Computer Science (LNCS)",

booktitle = "Proceedings of Field Programmable Logic and Applications",

}