Abstract
In this paper, we consider the SystemC-based open-source RISC-V VP++ with support for the RISC-V "V" Vector Extension (RVV), whose interpreter-based Instruction Set Simulator (ISS) has recently been significantly optimized, as presented in [1]. While the original paper examined simulation performance gains using classical, non-vectorized workloads, this paper focuses on the gains on a workload vectorized using RVV.
| Original language | English |
|---|---|
| Title of host publication | RISC-V Summit Europe 2025 |
| Number of pages | 2 |
| Edition | 1 |
| Publication status | Published - 2025 |
Fields of science
- 202028 Microelectronics
- 102011 Formal languages
- 202017 Embedded systems
- 102005 Computer aided design (CAD)
- 202041 Computer engineering
- 202005 Computer architecture
JKU Focus areas
- Digital Transformation