Extensive FPGA and ASIC resource comparison for blind I/Q imbalance estimators and compensators

In wireless communications, in-phase (I) and quadrature-phase (Q) imbalance is a well-understood issue, and an extensive body of different I/Q imbalance estimation and compensation algorithms exists in the literature. Many of these algorithms, including those in this work, focus on mitigating I/Q imbalance on the receiver side. We consider frequency-independent (FID) estimators that operate as so-called blind algorithms, where little to no knowledge about the transmitted data is required. However, little effort has been made to compare the required resources for implementing these algorithms in hardware. In this work, we compare a comprehensive list of such algorithms with regard to their logic utilization, required registers, and embedded multipliers when implementing them on a field-programmable gate array (FPGA). Subsequently, we provide synthesis results based on the SkyWater 130nm open-source process design kit (PDK), which enables comparisons of the required chip areas for the corresponding application-specific integrated circuit (ASIC) designs. We optimize the fixed-point bit-widths, and other hardware implementation specific parameters of the individual estimators to provide meaningful results. This optimization aims to achieve a common performance target for a typical orthogonal frequency-division multiplexing (OFDM) signal scenario.