Abstract
In this paper, we introduce Deep Reinforcement
Learning (DRL) for design cost optimization at early stages of
the System on Chips (SoCs) design process. We demonstrate
that DRL is a suitable solution for the problem at hand. We
benchmark three DRL algorithms based on Pointer Network, a
neural network specifically applied for combinatorial problems,
on the design cost optimization. We show that this lead to the
considerable improvements in cost optimization compared to
conventional optimization methods. Additionally, by using the
recently introduced RUDDER method and its reward redistribution approach, we obtain a significant improvement in complex
designs.
| Original language | English |
|---|---|
| Pages (from-to) | 43-51 |
| Number of pages | 9 |
| Journal | IEEE Design and Test |
| Volume | 40 |
| Issue number | 1 |
| Early online date | 2022 |
| DOIs | |
| Publication status | Published - 01 Feb 2023 |
Fields of science
- 102 Computer Sciences
- 202 Electrical Engineering, Electronics, Information Engineering
JKU Focus areas
- Digital Transformation