Abstract
Field-coupled Nanocomputing (FCN) devices
emerged as a post-CMOS alternative that promises highest
computation capabilities with lowest power dissipation. To
meet the strict FCN design rules, most existing physical design
techniques still rely on conventional methods from almost two
decades now - rendering the realization of large scale functions
infeasible. In this work, we propose an alternative approach to
the physical design of FCN circuits which bails on ineffective
methods like balancing. By this, we are able to generate FCN
circuit layout descriptions of functions for which state-of-the-art
methods timeout.
Original language | English |
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Title of host publication | IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Number of pages | 6 |
Publication status | Published - 2020 |
Fields of science
- 102 Computer Sciences
- 202 Electrical Engineering, Electronics, Information Engineering
JKU Focus areas
- Digital Transformation