Abstract
A key issue in pushing the digitization of Phase Locked Loops (PLLs) for RF transmitters is the realization of proper phase/frequency detectors in the digital domain. This paper presents a simulative analysis of the properties for and re-quirements of a two-bit frequency discriminator used for digitiza-tion of frequency in All Digital PLLs (ADPLLs) with two-point modulation. Effects due to reference clock jitter in one-bit and two-bit frequency discriminators are treated. Furthermore, meas-urement results for the synthesis mode of the ADPLL used in multi-mode capable terminal are given.
| Original language | English |
|---|---|
| Title of host publication | Proceedings European Conference on Wireless Technology |
| Pages | pp. 273-276 |
| Number of pages | 4 |
| Publication status | Published - 2006 |
Fields of science
- 202 Electrical Engineering, Electronics, Information Engineering
- 202019 High frequency engineering
- 202029 Microwave engineering
- 202030 Communication engineering
- 202033 Radar technology
- 202037 Signal processing
- 202038 Telecommunications