An Open-Source Adaptive Event-Based ADC for Bio-Signal Acquisition in 130nm CMOS

In nature, signals predominantly exist in analog form. However, efficient signal processing, such as amplification, filtering, extraction, or encryption of information, storage, and data compression, mainly occurs in the digital domain. Consequently, analog-to-digital converters (ADCs) are among the most essential components in electronic systems.
The most commonly used ADCs are so-called Nyquist ADCs, which operate at a fixed sampling frequency and thus output equidistant samples. However, certain signal groups exhibit significant variations only within short time intervals. This is particularly relevant in bio-signal acquisition and processing, where sparse signals are observed in electrocardiograms (ECGs) and electroencephalograms (EEGs). According to the Nyquist-Shannon sampling theorem, the sampling rate of a Nyquist ADC is determined by the highest frequency component during these transient changes. This results in an unnecessarily excessive number of samples in minimal signal variation time intervals, leading to higher power consumption in data processing and transmission.
However, optimizing data handling and energy consumption is crucial for battery-powered, wireless, and wearable devices, such as fitness trackers, medical sensors, and Internet of Things (IoT) devices. Event-based ADCs offer a promising solution by generating data points only when the signal exceeds a predefined voltage threshold. This work demonstrates that adaptively adjusting these voltage thresholds further enhances efficiency.
The first chapter motivates the use of event-based ADCs, discusses the advantages and limitations of free and open-source software (FOSS), and provides an overview of the tools used in this thesis. The IIC-OSIC-TOOLS all-in-one Docker container from the Institute for Integrated Circuits and Quantum Computing (IICQC) at Johannes Kepler University (JKU) and IHP's 130nm open-source process development kit (PDK) are utilized. All design files are openly available via a GitHub repository, whose organization is presented alongside references to YouTube tutorials on open-source IC design.
Chapter two presents the theoretical foundations of event-based ADCs, including aliasing, resolution, nonidealities, fixed-window and floating-window topologies, and diverse terminology found in literature. The concept of adaptive event-based ADCs is introduced and compared to Nyquist ADCs, followed by a discussion of reconstruction methods and their respective advantages and limitations.
Subsequently, in chapter three, a PCB-level demonstrator is developed to validate the feasibility of the event-based ADC concept. This setup consists of an analog front-end (AFE) PCB connected to an FPGA board. The demonstrator enables the development of a reconstruction framework for non-uniform data points in Matlab and Python and serves as a verification platform of the digital core. The digital core is tested on an Altera Cyclone V and a Xilinx Spartan 7 FPGA using Quartus Prime and Vivado Design Suite, respectively.
Chapters four and five define the system-level specifications and present the analog circuit design using Xschem, Ngspice, and Jupyter notebooks for gm/ID sizing scripts. This modern design methodology simplifies adaptation to different circuit specifications and eases migration to other PDKs by utilizing four-dimensional lookup tables. The fully-differential analog front-end consists of a bio-signal amplifier with capacitive feedback (CFA), a capacitive digital-to-analog converter (C-DAC), and two discrete-time (DT) comparators. Additional auxiliary circuits, such as up/down level shifters, Schmitt triggers, and ESD protection, are implemented to ensure a robust design.
Moreover, in chapter six, the digital design is written in VHDL and is explained with a block diagram. Since some open-source tools prefer Verilog, the VHDL code is converted using GHDL. Simulations are conducted with GTKWave, Surfer, or ModelSim, while register-transfer level (RTL) synthesis is performed using Yosys.
In chapter seven, the gate-level synthesized digital design is included in Xschem using qflow scripts and Xspice, enabling analog-mixed signal (AMS) simulations. First, the AMS simulation is carried out with ideal AFE components to extend the reconstruction framework for Ngspice-simulated UART data and to validate the digital core. In the end, the AMS simulation is performed with the transistor-level circuits.
Chapter eight focuses on generating the digital layout using OpenROAD Flow Scripts (ORFS) and evaluating it in terms of area utilization, power consumption, routing congestion, and timing performance. The layout of the analog design is beyond the scope of this thesis.
Finally, the last chapter outlines a pinout, suggests a suitable package, and proposes a potential evaluation board for the designed application-specific integrated circuit (ASIC).