An Open-Source 1.44-MS/s 703-μW 12-bit Non-Binary SAR-ADC Using 448-aF Capacitors in 130-nm CMOS

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Abstract

This paper presents the design of a self-clocked 12-bit non-binary fully differential SAR-ADC using the SKY130 open-source PDK. The entire mixed-signal circuit design and layout were created with free and open-source software. The ADC reaches a sample rate of up to 1.44MS/s at 1.8V supply while consuming 703µW of power on a small 0.175mm² area. A configurable decimation filter can increase the ADC resolution up to 16 bits while using an oversampling factor of 256. A 9-bit thermometer-coded and 3-bit binary-coded DAC matrix using a 448aF waffle-capacitor results in a total capacitance of 1.83pF per input. Realizations of configurable analog functions using the form factor of SKY130 high-density standard cells allow the parametrization of an analog circuit in a hardware description language and hardening of the macro in an intentionally digital workflow.
Original languageEnglish
Title of host publication2023 Austrochip Workshop on Microelectronics, Austrochip 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2-5
Number of pages4
ISBN (Electronic)9798350357851
DOIs
Publication statusPublished - Sept 2023
Event2023 Austrochip Workshop on Microelectronics, Austrochip 2023 - Graz, Austria
Duration: 20 Sept 202321 Sept 2023

Publication series

Name2023 Austrochip Workshop on Microelectronics, Austrochip 2023 - Proceedings

Conference

Conference2023 Austrochip Workshop on Microelectronics, Austrochip 2023
Country/TerritoryAustria
CityGraz
Period20.09.202321.09.2023

Fields of science

  • 202018 Semiconductor electronics
  • 202028 Microelectronics
  • 202027 Mechatronics
  • 202 Electrical Engineering, Electronics, Information Engineering
  • 102005 Computer aided design (CAD)
  • 202037 Signal processing
  • 202023 Integrated circuits
  • 202006 Computer hardware
  • 102 Computer Sciences

JKU Focus areas

  • Digital Transformation

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