A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform.

F. Eibensteiner, J. Kogler, Josef Scharinger

Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

Original language	English
Title of host publication	Proceedings of the 10th IEEE Embedded Vision Workshop (held in conjunction with IEEE CVPR), Columbus, USA.
Number of pages	4
Publication status	Published - 2014

Fields of science

@inproceedings{028363fdd1204b07ab6f1f2decda185f,

title = "A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform.",

author = "F. Eibensteiner and J. Kogler and Josef Scharinger",

year = "2014",

language = "English",

booktitle = "Proceedings of the 10th IEEE Embedded Vision Workshop (held in conjunction with IEEE CVPR), Columbus, USA.",

}

A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform. / Eibensteiner, F.; Kogler, J.; Scharinger, Josef.
Proceedings of the 10th IEEE Embedded Vision Workshop (held in conjunction with IEEE CVPR), Columbus, USA.. 2014.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review