A 6ps Resolution Pulse Shrinking Time-to-Digital Converter as Phase Detector in Multi-Mode Transceiver

Yue Liu; Ulrich Vollenbruch; Yangjian Chen; Christian Wicpalek; Linus Maurer; Zdravko Boos; Robert Weigel

A 6ps Resolution Pulse Shrinking Time-to-Digital Converter as Phase Detector in Multi-Mode Transceiver

Yue Liu, Ulrich Vollenbruch, Yangjian Chen, Christian Wicpalek, Linus Maurer, Zdravko Boos, Robert Weigel

Institute for Communications Engineering and RF-Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

Abstract

This paper presents a new phase detector in an all digital phase locked loop which converts the phase difference between one reference clock edge and one divided oscillator edge into a digital word. This digital word can be converted into a digital representation of the actual phase error which can be utilized in an all digital phase locked loop. 6 ps resolution for this Time-to-Digital Converter (TDC) is realized in a standard 0.13 μm CMOS technology. Its Full-Scale-Range (FSR) is 4500 ps.

Original language	English
Title of host publication	Proceedings of the IEEE Radio and Wireless Symposium
Number of pages	4
Publication status	Published - 2008

Fields of science

202 Electrical Engineering, Electronics, Information Engineering
202019 High frequency engineering
202029 Microwave engineering
202030 Communication engineering
202033 Radar technology
202037 Signal processing
202038 Telecommunications

Cite this

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title = "A 6ps Resolution Pulse Shrinking Time-to-Digital Converter as Phase Detector in Multi-Mode Transceiver",

abstract = "This paper presents a new phase detector in an all digital phase locked loop which converts the phase difference between one reference clock edge and one divided oscillator edge into a digital word. This digital word can be converted into a digital representation of the actual phase error which can be utilized in an all digital phase locked loop. 6 ps resolution for this Time-to-Digital Converter (TDC) is realized in a standard 0.13 μm CMOS technology. Its Full-Scale-Range (FSR) is 4500 ps.",

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AU - Vollenbruch, Ulrich

AU - Chen, Yangjian

AU - Wicpalek, Christian

AU - Maurer, Linus

AU - Boos, Zdravko

AU - Weigel, Robert

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AB - This paper presents a new phase detector in an all digital phase locked loop which converts the phase difference between one reference clock edge and one divided oscillator edge into a digital word. This digital word can be converted into a digital representation of the actual phase error which can be utilized in an all digital phase locked loop. 6 ps resolution for this Time-to-Digital Converter (TDC) is realized in a standard 0.13 μm CMOS technology. Its Full-Scale-Range (FSR) is 4500 ps.

M3 - Conference proceedings

BT - Proceedings of the IEEE Radio and Wireless Symposium

ER -