Abstract
A wide-frequency-range low-power synthesizer based on an eight-stage differential ring oscillator (RO) regulated by a phase locked loop (PLL) is introduced. It is specially designed to be used in edge-combining transmitters and fabricated in a 180nm 1P6M CMOS process. It provides 16 symmetrical phase-shifted outputs for up to 8-times frequency-multiplication using an external edge-combiner. The oscillator is implemented as current-starved RO. It includes a biasing network with threshold regulation for close to 50% duty cycle and equal time delay in all RO stages. The lower corner-frequency is 5 bit adjustable (50MHz to 300 MHz) and the oscillator offers an additional 5 bit trimmable tuning range (20.3MHz to 97.2 MHz). The structure is optimized to operate at 216MHz and shows a phase noise of −96 dBc/Hz at 1MHz offset as well as −76 dBc/Hz in-band phase noise (with locked PLL below 100 kHz offset). With its low power demand of 1.3mW, the frequency synthesizer is suited to be used in low-power transmitters.
| Original language | English |
|---|---|
| Title of host publication | 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) |
| Pages | 22-25 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781728170442 |
| DOIs | |
| Publication status | Published - 2020 |
Fields of science
- 102 Computer Sciences
- 202 Electrical Engineering, Electronics, Information Engineering