Project Details
Description
Realisation of an asic (complexity: 400 k gates) in 0.18 micron technology. Therefore the
memory blocks of the target technology (including a memory bist) are inserted in the design. Finally a verilog netlist of the design will be generated.
| Status | Finished |
|---|---|
| Effective start/end date | 01.07.2002 → 30.09.2002 |
Collaborative partners
- Johannes Kepler University Linz (lead)
- GE Medical Systems Kretztechnik GmbH & Co OHG (Project partner)
Fields of science
- 202028 Microelectronics
- 202037 Signal processing
- 202023 Integrated circuits
- 102003 Image processing
- 202027 Mechatronics
- 202018 Semiconductor electronics
- 202 Electrical Engineering, Electronics, Information Engineering
- 102005 Computer aided design (CAD)
- 202006 Computer hardware
JKU Focus areas
- Digital Transformation