Project Details
Description
HW implementation of high-speed algorithms for the real-time imageprocessing of 3D ultrasound images and subsequent Xilinx FPGA (Virtex) realization. System clock 60+ MHz. Core: dual, symmetrical FIR filter (16 Bit) with 32 taps.
| Status | Finished |
|---|---|
| Effective start/end date | 15.04.1999 → 15.02.2000 |
Collaborative partners
- Johannes Kepler University Linz (lead)
- Kretztechnik AG (Project partner)
Fields of science
- 202028 Microelectronics
- 202037 Signal processing
- 202023 Integrated circuits
- 202027 Mechatronics
- 202018 Semiconductor electronics
- 202 Electrical Engineering, Electronics, Information Engineering
- 102005 Computer aided design (CAD)
- 202006 Computer hardware
JKU Focus areas
- Digital Transformation