Project Details
Description
Development of synthesis libraries targeting the automated development of schematics on the abstraction level of gates as well as primitive storage units based on the usage of VHDL in an ASIC designflow.
| Status | Finished |
|---|---|
| Effective start/end date | 02.07.1997 → 30.11.1997 |
Collaborative partners
- Johannes Kepler University Linz (lead)
- AMS (Project partner)
Fields of science
- 202028 Microelectronics
- 202023 Integrated circuits
- 202027 Mechatronics
- 202018 Semiconductor electronics
- 202 Electrical Engineering, Electronics, Information Engineering
- 102005 Computer aided design (CAD)
- 202037 Signal processing
- 202006 Computer hardware
JKU Focus areas
- Digital Transformation