Project Details
Description
Evaluate the feasibility of a redesign of a complex signal-processsing asic (approx.400 kGates) and perform the redesign if it makes sense.
| Status | Finished |
|---|---|
| Effective start/end date | 15.01.2001 → 30.09.2001 |
Collaborative partners
- Johannes Kepler University Linz (lead)
- Kretztechnik AG (Project partner)
Fields of science
- 202028 Microelectronics
- 202037 Signal processing
- 202023 Integrated circuits
- 102003 Image processing
- 202027 Mechatronics
- 202018 Semiconductor electronics
- 202 Electrical Engineering, Electronics, Information Engineering
- 102005 Computer aided design (CAD)
- 202006 Computer hardware
JKU Focus areas
- Digital Transformation