Project Details
Description
VHDL modelling of a 8051-compatible macro cell for ASIC integration including verification, optimization of logic synthesis and test insertion.
| Status | Finished |
|---|---|
| Effective start/end date | 01.06.1996 → 28.02.1997 |
Collaborative partners
- Johannes Kepler University Linz (lead)
- FhG-IIS (Project partner)
Fields of science
- 202028 Microelectronics
- 202023 Integrated circuits
- 202027 Mechatronics
- 202018 Semiconductor electronics
- 202 Electrical Engineering, Electronics, Information Engineering
- 102005 Computer aided design (CAD)
- 202037 Signal processing
- 202006 Computer hardware
JKU Focus areas
- Digital Transformation