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Manfred Schlägl

DI, BSc

  • LIT Secure and Correct Systems Lab
  • Emailmanfred.schlaegljkuat
  • Overview
  • Network
  • Research output (9)
  • Activities (9)

Research output

  • 8 Conference proceedings
  • 1 Master's / Diploma thesis

Research output per year

Research output per year

  • Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes

    Schlägl, M. & Große, D., 2025, Design, Automation and Test in Europe (DATE) 2025. IEEE Xplore, 7 p. (Proceedings -Design, Automation and Test in Europe, DATE).

    Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

    Open Access
  • RVVTS: AModular, Open-Source Framework for Positive and Negative Testing of the RISC-V "V" Vector Extension (RVV)

    Schlägl, M. & Große, D., 2025, (Accepted/In press) ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2025. 3 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

  • A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level

    Schlägl, M., Stockinger, M. & Große, D., 2024, Design, Automation and Test in Europe Conference (DATE) 2024. 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

  • Bounded Load/Stores in Grammar-based Code Generation for Testing the RISC-V Vector Extension

    Schlägl, M. & Große, D., 2024, RISC-V Summit Europe 2024. 2 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

  • RISC-V VP++: Next Generation Open-Source Virtual Prototype

    Schlägl, M., Hazott, C. & Große, D., 2024, Workshop on Open-Source Design Automation (OSDA) 2024 hosted at DATE. 2 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review

View all 9 research outputs

Activities

  • 4 Contributed talk
  • 3 Poster presentation
  • 2 Invited talk

Activities per year

  • Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes

    Schlägl, M. (Speaker) & Große, D. (Speaker)

    02 Apr 2025

    Activity: Talk or presentation › Invited talk › science-to-science

  • RVVTS: AModular, Open-Source Framework for Positive and Negative Testing of the RISC-V "V" Vector Extension (RVV)

    Große, D. (Speaker) & Schlägl, M. (Speaker)

    11 Mar 2025

    Activity: Talk or presentation › Invited talk › science-to-science

  • Single Instruction Isolation for RISC-V Vector Test Failures

    Große, D. (Speaker) & Schlägl, M. (Speaker)

    29 Oct 2024

    Activity: Talk or presentation › Contributed talk › science-to-science

  • Bounded Load/Stores in Grammar-based Code Generation for Testing the RISC-V Vector Extension

    Große, D. (Speaker) & Schlägl, M. (Speaker)

    26 Jun 2024

    Activity: Talk or presentation › Poster presentation › science-to-science

  • A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level

    Schlägl, M. (Speaker), Stockinger, M. (Speaker) & Große, D. (Speaker)

    26 Mar 2024

    Activity: Talk or presentation › Contributed talk › science-to-science

View all 9 activities
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