Research output per year
Research output per year
-
A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture
Schlägl, M., Hinterdorfer, A. & Große, D., 10 Mar 2026, 31st Asia and South Pacific Design Automation Conference (ASP-DAC) 2026. 1 ed. p. 1230-1236 7 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review
-
ART: Autonomous Radar Transceiver Architecture for Cost-Optimized Satellite Radar Systems
Atzmüller, M., Findenig, R., Greslehner-Nimmervoll, B. & Große, D., 22 Jun 2026, GLSVLSI '26: Proceedings of the Great Lakes Symposium on VLSI 2026. Chen, F., Zhou, P., Gu, J., Trivedi, A. R. & Yang, X. (eds.). 1 ed. ACM, p. 730-736 7 p.Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review
Open Access -
Distinguishing Exploit Failure from Effective CHERI Protection on RISC-V
Hinterdorfer, A., Schlägl, M. & Große, D., 2026, (Accepted/In press) RISC-V Summit Europe 2026. 2 p.Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review
-
FastISS-Enhanced RISC-V VP++: Latest Results in High-Performance Interpreter-Based Simulation
Schlägl, M. & Große, D., 2026, (Accepted/In press) MBMV 2026 - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 29. Workshop. 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review
-
From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
Schlägl, M., Reichhardt, J. & Große, D., 22 Jun 2026, GLSVLSI '26: Proceedings of the Great Lakes Symposium on VLSI 2026. Chen, F., Zhou, P., Gu, J., Trivedi, A. R. & Yang, X. (eds.). 1 ed. ACM, p. 622-629 8 p.Research output: Chapter in Book/Report/Conference proceeding › Conference proceedings › peer-review
Open Access
-
ODE4EC-PIV: Open Design Ecosystem for European Chips - Productivity, Interoperability, Verification
Große, D. (PI)
01.06.2026 → 31.05.2029
Project: Funded research › EU - European Union
-
ODE4EC-DIG: Open Design Environment for European Chips - Digital SoC Design
Große, D. (PI)
01.06.2026 → 31.05.2029
Project: Funded research › EU - European Union
-
ENGEL Austria Gmbh
Große, D. (PI), Riegler, M. (Researcher), Stadler, M. (Researcher), Wille, R. (Researcher) & Sametinger, J. (Co-PI)
01.08.2019 → 31.07.2027
Project: Contract research › Industry project
-
Modular Real-Time Control
Atzmüller, M. (Researcher) & Große, D. (PI)
01.10.2023 → 30.09.2026
Project: Other › PhD thesis project
-
VerA: Fully Automatic Formal Verification of Arithmetic Circuits
Große, D. (PI)
01.11.2020 → 28.02.2023
Project: Funded research › Other mainly public funds
Activities
-
Research Chair of the Design and Verification Conference in Europe (DVCon Europe) (Event)
Große, D. (Member)
17 Nov 2026 → 18 Nov 2026Activity: Membership/Function › Program committee
-
Program Committee Member of the 34th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (Event)
Große, D. (Member)
11 Oct 2026 → 14 Oct 2026Activity: Membership/Function › Program committee
-
Program Committee Member of the Forum on specification & Design Languages (FDL) (Event)
Große, D. (Member)
09 Sept 2026 → 11 Sept 2026Activity: Membership/Function › Program committee
-
Program Committee Member of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (Event)
Große, D. (Member)
07 Jul 2026 → 09 Jul 2026Activity: Membership/Function › Program committee
-
ART: Autonomous Radar Transceiver Architecture for Cost-Optimized Satellite Radar Systems
Atzmüller, M. (Speaker), Findenig, R. (Speaker), Greslehner-Nimmervoll, B. (Speaker) & Große, D. (Speaker)
23 Jun 2026Activity: Talk or presentation › Poster presentation › science-to-science
Prizes
-
Best Paper Award: Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
Herdt, V. (Recipient), Große, D. (Recipient), Eyck, J. (Recipient) & Drechsler, R. (Recipient), Sept 2020
Prize: Prize, award or honor
-
Best Paper Award: Formal verification of SUBLEQ microcode implementing the RV32I ISA
Klemmer, L. (Recipient), Gurtner, S. (Recipient) & Große, D. (Recipient), Sept 2022
Prize: Prize, award or honor
-
Best Paper Candidate: Control flow protection by cryptographic instruction chaining
Ahmad, S. (Recipient), Rass, S. (Recipient), Goman, M. (Recipient), Schlägl, M. (Recipient) & Große, D. (Recipient), Jun 2025
Prize: Prize, award or honor
-
Best Paper Candidate: System Level Verification of Phase-Locked Loop Using Metamorphic Relations
Hassan, M. (Recipient), Große, D. (Recipient) & Drechsler, R. (Recipient), Feb 2021
Prize: Prize, award or honor