WSVA: A SystemVerilog Assertion to WAL Compiler

Description

SystemVerilog Assertions (SVA) is an industry standard for specifying properties that describe the correct behavior of a system. Compared to SystemVerilog’s immediate assertions, they provide a much more powerful syntax including the ability to specify properties spanning over multiple clock cycles. However, to the best of our knowledge, SVA is not supported by any available open-source Electronic Design Automation (EDA) tool. In this paper, we present WSVA, a compiler from SVA to the Waveform Analysis Language (WAL).

Period	25 Mar 2024
Event title	Workshop on Open-Source Design Automation (OSDA) 2024 hosted at DATE
Event type	Conference
Location	SpainShow on map