Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows

Description

The ever increasing complexity of modern circuits and systems remains a big challenge for the semiconductor industry. Since the life cycle of new products is getting smaller and smaller, companies have to speed-up their design flows to stay competitive. This particularly holds for the efforts spent to verify and test a chip. Here, the development of proper test programs to be executed on the fabricated chip constitutes a serious bottleneck. This is because the first application of the test program on actual silicon frequently unveils errors that need to be addressed – causing debugging loops and a threat to time-to-market objectives. Consequently, it is tried to conduct these tests earlier in the design flow, i.e. before first silicon is available. In this work, we propose a corresponding virtual test methodology which allows to test a test program on a virtual representation of the chip (e.g. a SystemC description which is available early in the design process anyway). In contrast to previously proposed solutions, our methodology can be integrated in a generic and black-box fashion into existing flows, i.e. the user does not need to know whether the test program is executed on actual silicon or its virtual description. A case study within an industrial environment confirms the benefits of the proposed methodology.

Period	15 Jul 2019
Event title	IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Event type	Conference
Location	United StatesShow on map