Simulation model based on JEDEC JS-001-2014 for circuit simulation of HBM ESD pulses on IC level

Description

A 3rd order lumped element circuit for the simulation of the JEDEC HBM ESD JS-001-2014 pulse is proposed. The resulting current pulse is analytically computed with a state space model of the circuit. For the purpose of verification a computer algebra system is used, solving and checking the model if it generates a current pulse which fulfils the requirements. The values of the voltage pulse, resistor, inductor and capacitor can be changed dynamically, resulting in an instant check against the standard which is also visualised by a plot. Results of the analytical solution s are compared against numerical simulation in SPICE.

Period	11 Nov 2015
Event title	10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)
Event type	Conference
Location	Edinburgh, United KingdomShow on map