RVVTS: AModular, Open-Source Framework for Positive and Negative Testing of the RISC-V "V" Vector Extension (RVV)

Description

In this extended abstract, we summarize the work from [1], where we presented the modular, open-source framework RVVTS for positive and negative testing of the RISC-V "V" Vector Extension (RVV) with its 600+ highly configurable instructions. The framework comes with a grammar-based, coverage-guided Instruction Sequence Generator (ISG), automation for instrumentation, build and run of test-cases, and the ability to detect differences in architectural states after runs. At the heart of the framework is our novel Single Instruction Isolation with Code Minimization technique which allows to reduce manual result analysis of failing test cases significantly. By applying RVVTS to the RISC-V VP++ Virtual Prototype and the QEMU emulator, we confirmed 3 new bugs in the RISC-V VP++ and 2 in QEMU (and 7 more are to be analyzed). RVVTS, as well as the pre-generated test sets are available as open-source on GitHub*

Period	11 Mar 2025
Event title	ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2025
Event type	Workshop
Location	Rostock/Warnemünde, GermanyShow on map