Low phase noise 77-GHz fractional-N PLL with DLL-based reference frequency multiplier for FMCW radars

Description

Two architectures of 77-GHz fractional-N phase-locked loops (PLLs) for FMCW radars are presented. Both architectures show good performance in terms of phase noise with -79 dBc/Hz at 100 kHz offset frequency. To achieve this, the integration of a delay-locked loop-based frequency multiplier for the reference signal in the PLL is proposed. It exhibits very low phase noise and proves to be an excellent alternative to other types of multipliers for lower frequencies.

Period	10 Oct 2011
Event title	European Microwave Integrated Circuits Conference 2011
Event type	Conference
Location	United KingdomShow on map