FPGA Processing of Decision Tree Ensembles Stored in External DRAM

Description

Ensemble methods are an interesting alternative to neural networks, especially due to their inherent parallelization capabilities. Forming ensembles from decision trees (e.g. in so- called random forests) has the additional advantage that process- ing a decision tree can be performed with low-complexity oper- ations. When compared to other machine learning approaches such as (deep) neural networks, tree-based ensemble methods can deliver similar accuracy while being considerably simpler in terms of implementation effort and computational complexity. A major challenge for implementation in resource-constrained hardware such as FPGAs are the memory requirements of decision trees. While on-chip memories on current FPGAs are typically very fast, the available space is often not enough for complex problems, leading to a need to integrate external dynamic memories into the system architecture. In this paper, we propose a hardware architecture and an accompanying subtree- based memory layout that considers the inherent problems of decision trees and the memories’ physical latency constraints to speed up the processing of decision tree ensembles by increasing the bandwidth efficiency of memory transfers. We show that this can increase the processing speed by up to 3.38 times when compared to a naive (linear) memory layout for a single tree and 3.72 in a parallel scenario. This way it enables efficiently implementing tree-based ensemble learners for practical problem sizes on FPGAs.

Period	19 Jul 2023
Event title	International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME 2023)
Event type	Conference
Location	SpainShow on map