Formal methods for ranking verification counterexamples through assumption mining / Prof. Dr. Ansuman Banerjee

Description

Unit testing and verification constitute an important step in the validation life cycle of large and complex multi-component designs. Many unit validation methods often suffer from the problem of false negatives, when they analyze a component in isolation and look for errors. It often turns out that some of the reported unit failures are infeasible, i.e. the valuations of the component input pa-rameters that trigger the failure scenarios, though feasible on the unit in isolation, cannot occur in practice considering the integrated design, in which the unit-under-test is instantiated. In this talk, we consider this problem in the context of a multi-component design, with a set of unit failures reported on a specific unit. We present an automated two-stage failure scenario classification and prioritiza-tion strategy that can filter out false negatives and cluster them accordingly. The use of classical artificial intelligence and program analysis techniques in conjunction with formal verification helps in developing new frameworks for reasoning and deduction, which appear promising for a wide varie-ty of problems.

Period	23 Feb 2018
Event type	Guest talk
Location	AustriaShow on map