FastISS RISC-V VP++: A Simulation Performance Evaluation of RVV Workloads

Description

In this paper, we consider the SystemC-based open-source RISC-V VP++ with support for the RISC-V "V" Vector Extension (RVV), whose interpreter-based Instruction Set Simulator (ISS) has recently been significantly optimized, as presented in [1]. While the original paper examined simulation performance gains using classical, non-vectorized workloads, this paper focuses on the gains on a workload vectorized using RVV.

Period	15 May 2025
Event title	RISC-V Summit Europe 2025
Event type	Conference
Location	Paris, FranceShow on map
Degree of Recognition	International