Einfluss von digitalen Layout-Varianten auf die Robustheit von ICs

Activity: Talk or presentation › Poster presentation › unknown

Description

In the present work the influence of different layout styles regarding the robustness of integrated circuits are analyzed. The differences (power ring, power stripes and on-chip decoupling capacitances with the filler cells) were analyzed us- ing electromagnetic interference measurement within the test chip as well as TEM-cell measurements according IEC 61697.
Period25 Sept 2013
Event titleZuverlässigkeit und Entwurf, 2013
Event typeConference
LocationGermanyShow on map

Fields of science

  • 202006 Computer hardware
  • 202028 Microelectronics
  • 102005 Computer aided design (CAD)
  • 202037 Signal processing
  • 202018 Semiconductor electronics

JKU Focus areas

  • Computation in Informatics and Mathematics
  • Nano-, Bio- and Polymer-Systems: From Structure to Function
  • Mechatronics and Information Processing