Counter-Based vs. Shift-Register-Based Signal Processing in Stochastic Computing

Description

Stochastic computing (SC) is an emerging computing technique that encodes a real-valued number into a random bit stream, representing a number as the probability of observing the bit one. This representation allows basic arithmetic operations to be realized with simple logic gates, for example an AND gate and a multiplexer realize a multiplier and a scaled adder, respectively. Moreover, the stochastic representation has a high fault tolerance to circuit noise and bit flips. These characteristics - low implementation complexity and high error tolerance - are especially interesting for efficient signal processing algorithms. Many promising signal processing applications of SC require a large number of additions, for example neural networks, the FIR Filter operation or the DFT/FFT computation. For such use cases, the state-of-the-art multiplexer-based adder suffers significant drawbacks, because of its inherent precision loss due to scaling. Non-scaled adders are a promising approach to overcome this problem. It has been shown that two-line encoding formats, signed magnitude (SM) and the two-line bipolar (TLB), are appropriate formats for the efficient implementation of non-scaled adders. In this contribution, we will provide a comprehensive comparison of the UCB and the SRB approach for the non-scaled adder using the TLB format. Moreover, we discuss the tradeoff between the SRB and UCB design in terms of hardware costs.

Period	20 Feb 2019
Event title	EUROCAST 2019
Event type	Conference
Location	SpainShow on map