An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs

Description

Caches are essential to achieve high performance in modern hardware designs as they bridge the performance gap between digital logic and memories. However, prior research for analyzing the cache performance does not support the designer during the cache implementation. In this paper, we present an extensible, automated, and f lexible methodology for analyzing cache performance during HDLdesign. Our approach works by monitoring cache interfaces based on waveforms from simulators, formal tools, or logic analyzers. Both, the generic cache analysis algorithm and the analysis metrics are design agnostic and can be reused across designs and design configurations. We demonstrate that our methodology is applicable throughout all stages of the hardware development cycle from the first test, to debugging, all the way to multi-million cycle simulations.

Period	05 Sept 2024
Event title	Forum on specification and Design Languages (FDL 2024)
Event type	Conference
Location	Stockholm, SwedenShow on map