An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle

Description

In this work, we present an exploration platform for microcoded RISC-V cores leveraging the One Instruction Set Computer (OISC) principle. Following the industry-proven virtual prototyping approach, we have realized our exploration platform by implementing an extensible and configurable Instruction Set Simulator (ISS). The developed ORISCV-ISS combines the advanced ecosystem of RISC-V with the ultimate minimalism of OISCs. ORISCV-ISS serves as development platform for both, hardware architecture and microcode procedures, and provides the basis for early design space exploration. Using ORISCV-ISS, we developed SUBLEQ microcode that is fully RISC-V compliant and ready to be run on real hardware. We evaluate how multiple hardware configurations and OISC extensions affect the performance, providing key information to balance between area savings and system performance.

Period	04 Jul 2022
Event title	IEEE Annual Symposium on VLSI
Event type	Conference
Location	CyprusShow on map