A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level

Description

In this paper we introduce the first free- and opensource SystemC TLM based RISC-V Virtual Prototype (VP) with support for the RISC-V "V" Vector Extension (RVV) Version 1.0. After an introduction to RVV, we present the integration of RVV and its 600+ instructions into an existing VP leveraging code generation for over 20k Lines of Code (LoC). Moreover, we describe the verification of the resulting VP using the Instruction Sequence Generator (ISG) FORCE-RISCV and the Instruction Set Simulator (ISS) riscvOVPsim. Our case studies demonstrate the benefits of the RVV enhanced VP for system-level evaluation. We present non-vectorized and vectorized variants of two common algorithms which are executed on the VP with varying parameters. We show that by comparing the number of simulated execution cycles, we can derive valuable assessments for the design of RVV microarchitectures.

Period	26 Mar 2024
Event title	Design, Automation and Test in Europe Conference (DATE 2024)
Event type	Conference
Location	Valencia, SpainShow on map