A Receiver with Adiabatic and Harmonically Enriched Double-Frequency N-Path Drive

Description

This work demonstrates how adiabatic switching can be used to reduce the power consumption in N-path-filter based receiver designs. Our approach eliminates the common drawback of switching a relatively large gate capacitance at RF and the resulting power consumption is removed through adiabatic switching within the N-path. To maintain good filtering and switching performance while avoiding interferer pulling of the oscillator, an integrated class-F VCO with enriched 3rd order harmonic operating at 2x the RF input frequency is used for divider-based IQ generation. Steering switches directly connect the IQ mixer switches to the oscillator tank for a tuned drive. To prove the principle, a test-chip was fabricated in a 1P6M 180nm CMOS technology. The receiver, including an LNA and PLL, consumes 5.2mW from a 1.2V supply. It provides a gain of 17.7 dB and a narrowband 1.3MHz filtering within the 868MHz and 915MHz SRD bands. An integrated 50 input match is used, trading increased NF for a minimum number of external components.

Period	31 May 2022
Event title	International Symposium on Circuits and Systems (ISCAS)
Event type	Conference
Location	United StatesShow on map