A linear Watt-Level Power Amplifier Implemented in 28 nm Standard CMOS Technology

Description

A linear two-stage power amplifier (PA) implemented in 28nm standard CMOS technology is presented. It employs a fully differential input matching network (IMN), a cascoded driver amplifier and a two-stage wideband interstage matching network. To generateWatt-level output power a stacked transistor array operates as transconductance (gm) amplifier. An on-chip output matching network (OMN) performs differential to single-ended conversion. Additional process-voltage-temperature (PVT) compensation and biasing circuitry is integrated. The whole chip has been protected using proper ESD structures. The PA achieves a power-added efficiency (PAE) of 33% and a saturated output power of 31.2dBm when operating at 1.75 GHz. Without applying digital predistortion (DPD) ACLR values of < -25 dBc at 26.5dBm in-band power can be achieved for UTRA RMC12k2 test signals. When using memoryless DPD the ACLR improves to < -38 dBc at +- 5 MHz. Maximum EVM value decreases from < 6.5% to < 1.7% when using DPD.

Period	06 Nov 2014
Event title	Microwave Conference (APMC), 2013 Asia-Pacific
Event type	Conference
Location	JapanShow on map