A DSL for Visualizing Pipelines: A RISC-V Case Study

Description

The number of available RISC-V cores is growing rapidly and the openness of RISC-V enabled even smaller teams to develop their own cores. However, the wide variety of RISC-V cores available today and the high modularity of the ISA makes it hard for development tools to keep up with the speed of development, as well as to provide first class support for this growing ecosystem. In this paper, we present a Domain Specific Language (DSL) for defining processor pipelines. With just a few lines of code in this DSL, information about RISC-V pipelines can be collected from simulation waveforms for further processing. As one application of this DSL, we present a web application that functions as a pipeline rendering backend, helpful for debugging and design understanding.

Period	13 Sept 2023
Event title	RISC-V Summit Europe 2023
Event type	Conference
Location	ItalyShow on map