A 16 nm FinFet power- and phase noise-scalable DCO using on-chip tapped inductor

Description

As emerging communication standards e.g. LTE and 5G increase the complexity of wireless transceiver designs, multiple local oscillators are needed to serve all different bands and constraints given by the various supported standards. One oscillator has to serve several bands with dedicated limits for phase noise and power consumption. These limits can vary a lot over the supported bands thus the most stringent specification dominates the oscillator circuit design which leads to a design-overhead in operating-conditions with more relaxed performance constraints. To overcome the overhead mentioned before, this work presents a Digitally Controlled Oscillator (DCO) with configurable power consumption and phase noise. The DCO design provides two different power/phase noise modes. By switching between two CMOS-cores, the DCO can be configured having either low power consumption and moderate phase noise performance or a higher power consumption but better phase noise performance while maintaining a constant figure of merit (FoM) of 184.9. The two cores are connected to different taps of the main inductor of the LC tank. Thus an inner core and an outer core can be defined, each of them operating in one of the two operation modes. The presented design in a 16 nm FinFet process achieves a tuning range of 25.89 % with a center-frequency of 4.86 GHz. The DCO can be either operated with a power consumption of 2.45 mW with a phase noise of -117.2 dBc/Hz @ 1 MHz offset, or with a power consumption of 1.25 mW with a phase noise of -114.2 dBc/Hz @ 1 MHz offset

Period	09 Sept 2019
Event title	7. Workshop der ARGE HFT
Event type	Conference
Location	AustriaShow on map