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A 15-bit 28nm CMOS fully-integrated 1.6W digital power amplifier for LTE IoT

  • Jörg Fuhrmann (Speaker)
  • José Moreira (Speaker)
  • Patrick Oßmann (Speaker)
  • Springer, A. (Speaker)
  • Robert Weigel (Speaker)
  • Pretl, H. (Speaker)

Activity: Talk or presentation › Contributed talk › science-to-science

Description

This paper presents a 15-bit digital power amplifier (DPA) with 1.6W saturated output power. The topology of the polar switched-current DPA is discussed together with the architecture of the output transformer which is implemented in BEOL as well as in WLCSP metal layers. The chip is fabricated in a standard 28nm CMOS process and exhibits an EVM of 3.6%, E-UTRA ACLR of 34.1dB, output noise of -145.7dBc/Hz at 45 MHz offset and 22.4% DPA efficiency when generating a 26.8dBm LTE-1.4 output signal at 2.3GHz. The total area of the DPA is 0.5mm2.
Period12 Sept 2017
Event titleESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Event typeConference
LocationBelgiumShow on map

Fields of science

  • 202 Electrical Engineering, Electronics, Information Engineering
  • 102 Computer Sciences

JKU Focus areas

  • Nano-, Bio- and Polymer-Systems: From Structure to Function
  • Mechatronics and Information Processing

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