On Power ESD Test of Integrated Circuits

In addition to the ESD characterization of unpowered integrated circuits, especially in the case of hard failures, an ESD characterization of powered ICs is necessary in order to analyze possible soft failures. Especially since these soft failures occur although ESD protection elements are used in the IOs/padframe. To analyze the different coupling paths in the ICs, in addition to a corresponding modeling for the simulation, a check of the adaptation of the simulation to a suitable ESD measurement is required. The present paper deals with the possibilities of analyzing ESD events within a powered IC with suitable modeling and measurement methods.