High-Accuracy and Fault Tolerant Stochastic Inner Product Design

In this brief, we present a novel inner product (IP) design for stochastic computing (SC). SC is an emerging computing technique, that encodes a number in the probability of observing a one in a random bit stream. This leads to reduced hardware costs and high error tolerance. The proposed IP design is based on a two-line bipolar encoding format and applies sequential processing of the input in a central accumulation unit. Sequential processing significantly increases the computation accuracy, since it allows for preliminary cancelation of carry bits. Moreover, the central accumulation unit gives a much better scalability compared to conventional adder tree approaches. We show that the proposed IP design outperforms a state-of-the-art design in terms of hardware costs for high accuracy requirements and fault tolerance.