CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection

Memory corruption bugs are among the oldest and most persistent problems in computer security. Although modern type-safe programming languages attempt to address this problem, billions of lines of existing C and C++ code in performance critical applications will not be replaced in the foreseeable future. This had led to the development of Capability Hardware Enhanced RISC
Instructions (CHERI), a research project that extends conventional Instruction Set Architectures (ISAs), compilers and Operating Systems (OSs) with new architectural features for fine-grained memory protection. CHERI has been realized in several hardware prototypes and a QEMU based emulator with CHERI support is already available. However, no CHERI-enabled Virtual Prototype
(VP) has been published to date.
The contribution of this thesis is the design, implementation, verification and evaluation of CHERI-RISC-V VP++, a CHERI-enabled VP based on the open-source RISC-V VP++ project. This VP is capable of running unmodified CHERI-enabled software, including the capabilityenabled FreeBSD OS, called CheriBSD. The implementation was verified using random testing with the TestRIG framework and demonstrated through bare-metal CHERI-enabled programs, before successfully booting CheriBSD. The resulting CHERI-RISC-V VP++ is publically available and provides a cycle-approximate and deterministic platform for system-level evaluation of CHERI, offering a valuable tool for early design space exploration and advancing CHERI research.