Low-Power Digital-Intensive Receiver Architectures for Next Generation Narrowband Communication Systems

The growing demand for flexible, reconfigurable, and power-efficient receiver architectures in narrowband communication systems, such as Bluetooth Low Energy (BLE), has accelerated the push toward Software-Defined Radio (SDR) architectures. Traditional analog-intensive receiver designs face significant challenges in meeting the stringent requirements for power efficiency and performance, particularly while retaining scalability and adaptability to diverse use cases. In contrast, digital-intensive receiver architectures provide a compelling alternative by transitioning much of the signal processing workload to the digital domain. This shift not only reduces power consumption but also enhances system integration, scalability, and design flexibility.

This research aims to investigate and advance the state-of-the-art in low-power CMOS-based receiver architectures, with a particular focus on discrete-time and digital-intensive designs. Emphasis will be placed on comprehensive system-level analysis, modeling, and simulation to uncover the performance limits of such architectures. Building on these insights, the work will propose innovative solutions through advanced signal processing techniques, addressing critical hardware limitations. By introducing novel architectures and overcoming existing challenges, this research aspires to make significant contributions to the development of highly optimized receiver designs for BLE and other narrowband communication systems.