Using Formal Verification Methods for Optimization of Circuits under External Constraints

Beschreibung

This paper targets the optimization of circuit netlists by eliminating redundant gates under given external constraints. Typical examples for external constraints– which can be viewed as external don’t cares– are restrictions on input operands, instruction subsets used by a processor for specific applications, or limited operation modes of an integrated IP block. Targeting external don’t cares presents a challenge because the optimization problem changes from a completely specified Boolean function to a Boolean relation. We propose an optimization approach that utilizes formal verification methods. We demonstrate how to formulate Property Checking (PC) and Equivalence Checking (EC) problems to determine if a gate is redundant under given external constraints. Essentially, the validity of up to four rules must be checked per gate. We show that these checks can be solved concurrently, resulting in faster overall optimization. We have implemented our approach as the tool Formal SYNthesis (FSYN). FSYN utilizes open-source tools to scale the solving of formal instances with available hardware resources. We demonstrate that our approach can achieve substantial reductions in the number of gates for combinational circuits under given external constraints.

Zeitraum	25 März 2024
Ereignistitel	Design, Automation and Test in Europe Conference (DATE 2024)
Veranstaltungstyp	Konferenz
Ort	Valencia, SpanienAuf Karte anzeigen