A 180-nm 1.2-V LO Divider with Quadrature Phase Generation for Low-Power 868–915MHz SRD-Band Applications

Beschreibung

This paper proposes an LO-divider circuit with nonoverlapping quadrature phase generation in 180nm triple-well CMOS. It addresses the problem of dealing with a reduced supply voltage for power reduction, but still maintaining a sufficient maximum operating frequency for radio-frequency applications. The clock division and phase generation is done by using cross-connected D-latches. A brief overview of different latch architectures is given and compared concerning their power consumption and maximum frequency. Simulation results of an RC-extracted layout are presented, which show a current consumption of 400 μA at 868MHz output frequency.

Zeitraum	27 Sep. 2018
Ereignistitel	Austrochip 2018
Veranstaltungstyp	Konferenz
Ort	ÖsterreichAuf Karte anzeigen