A 15-bit 28nm CMOS fully-integrated 1.6W digital power amplifier for LTE IoT

Beschreibung

This paper presents a 15-bit digital power amplifier (DPA) with 1.6W saturated output power. The topology of the polar switched-current DPA is discussed together with the architecture of the output transformer which is implemented in BEOL as well as in WLCSP metal layers. The chip is fabricated in a standard 28nm CMOS process and exhibits an EVM of 3.6%, E-UTRA ACLR of 34.1dB, output noise of -145.7dBc/Hz at 45 MHz offset and 22.4% DPA efficiency when generating a 26.8dBm LTE-1.4 output signal at 2.3GHz. The total area of the DPA is 0.5mm2.

Zeitraum	12 Sep. 2017
Ereignistitel	ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Veranstaltungstyp	Konferenz
Ort	BelgienAuf Karte anzeigen